Chip identification using top metal layer

ABSTRACT

An integrated circuit (IC) structure includes a semiconductor substrate having a plurality of memory bits including IC identification information and a plurality of alternating metal and via layers thereabove. The IC structure includes a bond pad layer formed over a top one of the metal layers. The bond pad layer includes a plurality of pins connected to respective ones of the plurality of memory bits through the metal and via layers, at least one first pad connected to a higher voltage power supply rail and at least one second pad is connected to a lower voltage power supply rail. The bond pad layer has a plurality of circuit segments therein that each connects a respective one of the plurality of pins to either the at least one first pad or the at least one second pad for programming the IC identification information into the memory bit corresponding to that pin.

FIELD OF THE INVENTION

The present invention relates to integrated circuit (IC) structures andmethods of making the same, and more particularly to IC structureshaving identification and other product information provided therein.

BACKGROUND

Many integrated circuits have chip function identification codesprogrammed into the chip. The identification codes often take the formof thirty-two (32) bit codes that are programmed into the chip'scircuitry by selective connection of individual pins within the IC toVSS or VDD to represent data “0” or “1”, respectively. The pins areconnected to internal data circuitry, such as a register, formed in thesubstrate that can be accessed to read the 32 bit code programmed intothe chip. In these prior art chips, each bit design has a horizontalstrap with contacts and links on all metal levels. Each strap representsone metal level where the links can be removed and added depending onthe setting of the bit to VDD (high) or VSS (low).

FIG. 1 is a top view of a chip having a chip function identificationlayout using links within the metal layers for Bit 31 through Bit 0. Allmetal layers are shown. The area assigned to one bit is labeled as suchin FIG. 1. FIG. 2 is an enlarged view of the bit area shown in FIG. 1.The VSS and VDD rails are labeled as such. FIG. 3 is a cross-sectionalrepresentation of one bit area. FIG. 3 shows a pin formed at Metal 3that is connected by a circuit path (not shown) to substrate circuitry(e.g., a register) (also not shown). FIG. 3 also illustrates Metal andVia layers 1 to 7. Metal links 10 shown in FIG. 3 are selectivelyprovided or not provided on a specific metal level in order to set thebit of the chip ID to either LOW/VSS or HIGH/VDD, i.e., to selectivelyconnect the pin for that bit to VSS or VDD. Setting the links 10 in thisdesign is complex, since the designer must be sure to add and remove thecorrect metal link in the correct horizontal strap. Further, as newversions of the chip are released, new chip function identificationcodes are assigned to the new versions. Since the codes are programmedinto the chip using links 10 within the various metal connection layers,a new mask or masks (in some circumstances) is required to incorporatethe change in links needed to change the programmed bits of the code.This is required even if the change in chip functionality did notnecessitate a change to the structure of the metal/via connectionlayers. As those in the art will recognize, these metal layer masks arequite expensive, often costing $50,000 or more each, and difficult todesign.

New layout structures for programming chip identification function codesand other information are desired.

SUMMARY OF THE INVENTION

An integrated circuit (IC) structure includes a semiconductor substratehaving a plurality of memory bits and a plurality of alternating metallayers and via layers thereabove. The memory bits include ICidentification information. The IC structure includes a bond pad layerformed over a top one of the metal layers. The bond pad layer includes aplurality of pins connected to respective ones of the plurality ofmemory bits through the metal and via layers. At least one first pad isconnected to a higher voltage power supply rail and at least one secondpad is connected to a lower voltage power supply rail. The bond padlayer has a plurality of circuit segments therein where each of theplurality of circuit segments connects a respective one of the pluralityof pins to either the at least one first pad or the at least one secondpad for programming the IC identification information into the memorybit corresponding to that pin.

A method is also provided. The method includes the steps of providing asemiconductor substrate having a plurality of memory bits and aplurality of alternating metal layers and via layers thereabove, thememory bits including integrated circuit (IC) identificationinformation; forming a bond pad layer over a top one of the metallayers, the bond pad layer including at least one first pad connected toa higher voltage power supply rail and at least one second pad connectedto a lower voltage power supply rail; forming, in the bond pad layer, aplurality of pins connected to respective ones of the plurality ofmemory bits through the metal and via layers; and forming a plurality ofcircuit segments in the bond pad layer, each of the plurality of circuitsegments connecting a respective one of the plurality of pins to eitherthe at least one first pad or the at least one second pad, forprogramming the IC identification information into the memory bitcorresponding to that pin.

The above and other features of the present invention will be betterunderstood from the following detailed description of the preferredembodiments of the invention that is provided in connection with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings illustrate preferred embodiments of theinvention, as well as other information pertinent to the disclosure, inwhich:

FIG. 1 is a top view of a portion of prior art chip functionidentification layout using links within the metal layers;

FIG. 2 is an enlarged view of a portion of the layout of FIG. 1;

FIG. 3 is a cross-sectional representation of one bit from the layout ofFIGS. 1 and 2;

FIG. 4 is a top view of a portion of a chip using the top bond pad layerfor programming chip function identification information according tothe present invention;

FIG. 5 is a top view of a portion of the top bond pad layer of the chipof FIG. 4;

FIG. 6 is an enlarged view of a portion of the top view of FIG. 4;

FIG. 7 is a cross-sectional representation of the portion of FIG. 6; and

FIG. 8 is a top view of a portion of a chip having human-readableinformation provided in the top bond pad layer of the chip.

DETAILED DESCRIPTION

This description of the exemplary embodiments is intended to be read inconnection with the accompanying drawings, which are to be consideredpart of the entire written description. In the description, relativeterms such as “lower,” “upper,” “horizontal,” “vertical,” “above,”“below,” “up,” “down,” “top” and “bottom” as well as derivative thereof(e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should beconstrued to refer to the orientation as then described or as shown inthe drawing under discussion. These relative terms are for convenienceof description and do not require that the apparatus be constructed oroperated in a particular orientation. Terms concerning attachments,coupling and the like, such as “connected” and “interconnected,” referto a relationship wherein structures are secured or attached to oneanother either directly or indirectly through intervening structures, aswell as both movable or rigid attachments or relationships, unlessexpressly described otherwise.

A new method for programming chip identification information into anintegrated circuit chip and layout for accommodating this method aredescribed in connection with FIGS. 4-7. Though described in connectionwith programming chip identification information, it should beappreciated that the method and structure described herein can be usedto program any kind of information into a chip. FIG. 4 is a top view ofa chip with programming capability in the form of programmable linksbuilt into the top aluminum (or other conductive material) bond padlayer rather than the underlying metal interconnection layers asdescribed in the Background section. All mask layers are shown in FIG.4. As described below, pins are formed within the top bond pad layer andselectively coupled to high or low supply pads to perform programming.FIG. 5 provides a top plan view of the top aluminum bond pad layer. FIG.6 is an enlarged view of a portion of FIG. 4 focusing on the structurecorresponding to one bit. Finally, FIG. 7 is a cross-sectional view ofthe bit region of FIG. 6 illustrating various layers in the structurefor programming the chip identification information into the chipcircuitry.

As will be understood by those familiar with chip designs, the chipincludes a substrate having a metallization structure formed over thesubstrate including a plurality of metal layers and interconnectingmetal vias between the layers. Circuits are formed within the substrateusing known techniques. In embodiments, the substrate includes circuitryfor storing, at least while power is supplied to the chip, memory bits.In specific embodiments, these memory bits store chip functionidentification information. These memory bits can take the form of, forexample, a register formed from known transistor structures formed inthe substrate. This memory structure, sometimes referred to herein as“circuitry”, is coupled to pins for setting the data of the variousbits. This data can then be read from the register to read the data outof the chip.

Turning to FIG. 4, a layout 100 is shown for programming 32 bits of chipfunction identification information into the chip. Individual memorybits are programmed to either high (VDD) or low (VSS) by selectivelyconnecting a corresponding pin formed in the top aluminum bond pad layer(labeled AP in FIG. 7) to either a VDD pad or a VSS pad formed in the APlayer. “AP” stands for “Aluminum for bond pad” and is the top levelmetal in an IC. As more clearly shown in FIG. 5, the bond pad layer 150includes VDD pads 102 spaced from one another in a strip pattern andformed in a first line and VSS pads 104 spaced from one another andformed in a second line, which is parallel to and spaced from the firstline. In embodiments, the VDD and VSS pads can be continuous strips orspaced pads as shown. Individual pins are formed in the bond pad layer,although only pins B0 to B4, B7-B8, B11-B12, B15-B16, B19-B20, B23-B24,and B27-B31 are labeled in FIG. 4 and only pins B0-B5, B7 and B28-B31are labeled in FIG. 5. As can be seen from FIG. 5, the pins B0-B31 arealso formed in lines, including pins B0, B4, B8, B12, B16, B20, B24 andB28 in a first group, pins B1, B5, B9, B13, B17, B21, B25 and B29 in asecond group, pins B2, B6, B10, B14, B18, B22, B26 and B30 in a thirdgroup, and pins B3, B7, B11, B15, B19, B23, B27 and B31 in a fourthgroup. Each line of pins is formed in the bond pad layer adjacent to andin between a line of VDD pads 102 and a line of VDD pads 104.

Links are selectively formed between a given pin and an adjacent VDD pad102 or VSS pad 104 in order to connect the given pin to either a VDD orVSS pad. As shown in FIG. 5, links 106 are formed to connect a pin, suchas pin B0, B1, B3 or B31, to an adjacent respective VSS pad 104.Conversely, links 108 are formed to connect a pin, such as pin B2 or B4to an adjacent respective VDD pad 102. Not all links 106, 108 or pinsB0-B31 are labeled, so as to avoid unnecessary cluttering of theillustration of FIG. 5.

FIG. 6 shows an enlarged top view of a portion of FIG. 4 showing theconnection structure for programming Bit 3. As can be seen in FIG. 6,the pin B3 formed in the bond pad layer is connected to a correspondingVSS pad 104 by a link 106 formed in the bond pad layer. No link 108 isprovided. Therefore, pin B3 is set to VSS (i.e., low) when the chip ispowered on.

FIG. 7 is a cross-sectional view of the connection structure forprogramming a bit. Metal and via layers 6, 7 and 8 are shown in thecross sectional view. Higher power supply rail (VDD) 112 is provided atMetal 7 and lower power supply rail (VSS) 110 is also provided at Metal7. It should be understood that the VSS and VDD rails are shown at Metal7 merely for illustrative purposes and these rails can be formed atother metal layers as desired. These rails are connected through layersVia 7 and Metal 8 to the redistribution via (RV) layer to connect to VDDpad 102 and VSS pad 104 formed in the bond pad layer (labeled “AP”). Ascan be seen in the cross section, VSS pad 104 is connected to pin B3 viaan AP link 106 formed therebetween. For illustrative purposes only, FIG.7 shows that an AP link 108 would be formed between VDD pad 102 and pinB3 if it were desired to alternatively connect pin B3 to VDD link 102.In such an embodiment, AP link 106 would not be provided. Pin B3 isconnected in a vertical line through RV, Metal 8, Via 7, Metal 7, Via 6to Metal 6. Metal 6 is coupled by means of a circuit path through themetallization structure (not shown) to memory circuitry (e.g., registrycircuitry) formed in the substrate of the chip. Those of ordinary skillin the art will understand that the circuit path to the substratethrough the metal layers overlying the substrate can be designed in anynumber of ways. As illustrated, the connection structure between the pinB3 and an intermediate metal level (e.g., Metal 6) is purely vertical.

As described above, the selective programming of a bit to HIGH or LOW isaccomplished in the bond pad layer formed over the metal/viainterconnection layers of a chip. In the event that the 32 bit chipfunction identification code is changed, such as for a new version of achip, only the mask used in forming the bond pad layer need be changed.The mask for forming the bond pad layer is typically a very low costglass mask that is much less complicated than metal and via layer masks.These bond pad layer masks often cost twenty or more times less thanmetal and via layer masks and are much less difficult to modify fromdesign to design. The AP layer mask is the most cost effective mask towrite and thus to modify and the links of the AP layer mask—a maskgeometry that can be added or removed to connect a standard input to adifferent signal potential—are easy to design. With previous methods, ifchip functionality updates did not otherwise require changes tometal/via masks but the programming of the chip ID function code wasmade through links selectively set through the metal/via layers, thedesigner was nonetheless required to update at least one metal/vialayer. This step required the design and ordering of a completely newmask despite the fact that the functionality of the chip was not updatedthrough changes to the metal/via layers. With the present invention, inthe event that the updates to the chip functionality do not necessitatechanges to the metal/via structure, changes need only be made to themask used in forming the bond pad layer.

FIG. 8 is a top plan view of another portion of the bond pad (AP) layer,labeled 200. As can be seen in FIG. 8, the AP layer 200 also includesvarious human-readable features formed in the bond pad layer over themetal/via layers. The human-readable characters are approximately 22microns by 34 microns in size. These characters are formed by the padmaterial (e.g., aluminum) used in forming the pads 102, 104, pins B0-B31and links 106, 108. In the illustrated embodiment, the human-readableinformation includes a first human readable pattern indicating a productdevelopment number 230, a second human readable pattern indicating acopyright notice 210, and/or a third human readable pattern indicating amaskwork registration notice 220. Some or all of this information orother information (e.g., U.S. or foreign patent numbers, trademarks,etc.) can be written into the bond pad layer as desired using the samemask used to form the features in the bond pad layer discussed above inconnection with FIGS. 4-7. In prior art methods, this information waswritten/formed within multiple layers within the metal and via layers,or even at the substrate oxide layer, in an area of the chip void of anycircuitry, such as using the Virtuoso® Layout Tool available fromCadence Design Systems Inc. of San Jose, Calif. These feature charactersof the prior art are much smaller than those shown in FIG. 8, e.g.,approximately 12 microns by 17 microns. The use of the metal and vialayers or substrate oxide layer for these features necessitated updatingof the expensive masks for these layers if the information changed. Asdescribed above, one advantage of providing this information in the APlayer is that only the less expensive AP layer mask need be updated inthe event the human-readable information is changed or updated. Further,the larger character and closer proximity to the top layer of the chipmakes the AP layer information more readable than prior artcounterparts. Still further, all of the human-readable information canbe written in a single layer, requiring the use of only one mask.Finally, and importantly, the information written into the AP layer canbe formed anywhere on the chip including directly over the chip'scircuitry and interconnections because the design is not integrated intothe interconnection, or into the substrate oxide layer, saving chipsilicon area used in the prior art.

Although the invention has been described in terms of exemplaryembodiments, it is not limited thereto. Rather, the appended claimsshould be construed broadly, to include other variants and embodimentsof the invention, which may be made by those skilled in the art withoutdeparting from the scope and range of equivalents of the invention.

1. An integrated circuit (IC) structure, comprising: a semiconductorsubstrate having a plurality of memory bits and a plurality ofalternating metal layers and via layers thereabove, the memory bitsincluding IC identification information; and a bond pad layer formedover a top one of the metal layers, the bond pad layer including aplurality of pins connected to respective ones of the plurality ofmemory bits through the metal and via layers, at least one first padconnected to a higher voltage power supply rail and at least one secondpad connected to a lower voltage power supply rail, the bond pad layerhaving a plurality of circuit segments therein, each of the plurality ofcircuit segments connecting a respective one of the plurality of pins toeither the at least one first pad or the at least one second pad forprogramming the IC identification information into the memory bitcorresponding to that pin.
 2. The IC structure of claim 1, wherein eachof the plurality of pins is located between and adjacent to the at leastone first pad and the at least one second pad.
 3. The IC structure ofclaim 2, wherein the at least one first pad includes a plurality of padsarranged along a first line, the at least one second pad includes aplurality of pads arranged along a second line parallel to the firstline, and the plurality of pins are arranged in a third line between andparallel to the first and second lines.
 4. The IC structure of claim 1,wherein the bond pad layer is a single layer having pins for programmingall of the IC identification information into the memory bits of thesemiconductor substrate.
 5. The IC structure of claim 1, wherein themetal layers include circuit paths, and the via layers include vias forconnecting circuit paths formed in adjacent metal layers, and each ofthe plurality of pins is coupled to aligned vias in a plurality of vialayers forming a straight vertical path between the pin an intermediatemetal layer.
 6. The IC structure of claim 1, wherein the bond pad layerfurther comprises a human readable pattern indicating a productdevelopment number.
 7. The IC structure of claim 1, wherein the bond padlayer further comprises a human readable pattern indicating a copyrightnotice.
 8. The IC structure of claim 1, wherein the bond pad layerfurther comprises a human readable pattern indicating a maskworkregistration notice.
 9. The IC structure of claim 1, wherein the bondpad layer further comprises a human readable pattern indicating a numberof a patent that covers an IC that includes the IC structure.
 10. The ICstructure of claim 1, wherein the metal layers include circuit paths,and the via layers include vias for connecting circuit paths formed inadjacent metal layers, and wherein the bond pad layer further includesat least one human readable pattern showing information relating to theIC structure, wherein said human readable pattern is formed directlyover the circuit paths.
 11. A method, comprising: providing asemiconductor substrate having a plurality of memory bits and aplurality of alternating metal layers and via layers thereabove, thememory bits including integrated circuit (IC) identificationinformation; forming a bond pad layer over a top one of the metallayers, the bond pad layer including at least one first pad connected toa higher voltage power supply rail and at least one second pad connectedto a lower voltage power supply rail; forming, in the bond pad layer, aplurality of pins connected to respective ones of the plurality ofmemory bits through the metal and via layers; and forming a plurality ofcircuit segments in the bond pad layer, each of the plurality of circuitsegments connecting a respective one of the plurality of pins to eitherthe at least one first pad or the at least one second pad, forprogramming the IC identification information into the memory bitcorresponding to that pin.
 12. The method of claim 11, furthercomprising using a single mask to form the plurality of pins, the atleast one first pad, the at least one second pad, and the plurality ofcircuit segments, in the bond pad layer.
 13. The method of claim 12,further comprising using the single mask to form a human readablepattern indicating a product development number in the bond pad layer.14. The method of claim 12, further comprising using the single mask toform a human readable pattern indicating a copyright notice in the bondpad layer.
 15. The method of claim 12, further comprising using thesingle mask to form a human readable pattern indicating a maskworkregistration notice in the bond pad layer.
 16. The method of claim 12,further comprising using the single mask to form a human readablepattern in the bond pad layer indicating a patent that covers an ICstructure.
 17. The method of claim 11, wherein the metal layers includecircuit paths, and the via layers include vias for connecting circuitpaths formed in adjacent metal layers, the method further comprising thestep of forming at least one human readable pattern showing informationrelating to an IC structure, wherein said human readable pattern isformed directly over the circuit paths.
 18. The method of claim 11,wherein the step of forming the plurality of pins includes forming eachof the plurality of pins between and adjacent to the at least one firstpad and the at least one second pad.
 19. The method of claim 18, whereinthe at least one first pad comprises a plurality of first pads arrangedalong a first line, and the at least one second pad comprises aplurality of second pads arranged along a second line, and the pluralityof pins are arranged in a third line between and adjacent to the firstand second lines.
 20. The method of claim 11, further comprisingprogramming all of the IC identification information for the memory bitsusing a single mask.